1. Field of the Disclosure
This disclosure relates to photolithography simulation, and more specifically to simulation of optical scattering during mask photolithography simulation.
2. Description of the Related Art
In transferring a design layout (e.g. a circuit design layout) to a lithography mask, the mask writer will introduce parasitic distortions such as corner rounding, even with mask error correction. To properly simulate the distortions of the mask writer during optical proximity correction (OPC) and verification, the input to the simulation process is often in the form of mask contours (curved shapes) instead of sharp layout polygons. Additionally, optical scattering caused by sub-wavelength geometries in the mask will cause further distortions in the final design. The effect of this optical scattering may be referred to as the 3D mask effect. During OPC and verification simulation, the 3D mask effect should also be compensated for based on the more accurate mask contours. For full-chip applications like OPC and verification, it is important to simulate these two effects simultaneously with acceptable speed.